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15.4.8
Interrupt Level Register 4 (IRLVL4)
31
Reserved
15
Reserved
Bit
Mnemonic
Field Name
⎯
31:27
26:24
IL25
Interrupt level 25
⎯
23:19
18:16
IL24
Interrupt level 24
⎯
15:11
10:8
IL9
Interrupt level 9
⎯
7:3
27
26
24
IL25
R/W
000
11
10
8
IL9
R/W
000
⎯
Reserved
Interrupt Level of INT [25] (Default: 000, R/W)
These bits specify the interrupt level of ACLCPME interrupts.
000: Interrupt level 0 (Interrupt disabled)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Interrupt Level of INT [24] (Default: 000, R/W)
These bits specify the interrupt level of ACLC interrupts.
000: Interrupt level 0 (Interrupt disabled)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Interrupt Level of INT [9] (Default: 000)
These bits specify the interrupt level of SIO [1] interrupts.
000: Interrupt level 0 (Interrupt disabled)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Figure 15.4.8 Interrupt Level Register 4 (1/2)
15-24
Chapter 15 Interrupt Controller
0xF620
23
19
Reserved
7
3
Reserved
Explanation
18
16
IL24
R/W
: Type
000
: Default
2
0
IL8
R/W
: Type
000
: Default
Read/Write
⎯
R/W
⎯
R/W
⎯
R/W
⎯
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