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<Conditions>
This problem occurs when the following conditions are satisfied.
(1) The broken master detection function is enabled (BMCEN=1).
The broken master detection function is enabled or disabled with the BMCEN bit of the PCI bus
arbiter configuration register (PBACFG). The default value is 0 which disables the function.
(2) The bus masters are assigned to the high level and low level in the on-chip PCI bus arbiter.
The bus master is assigned to the bus arbiter with the PCI Bus Arbiter Request Port Register
(PBAREQPORT).
(3) When the PCI bus master connected to the high level is detected as the broken master, the master
connected to the low level requests the bus mastership, which is the highest-priority request in the
low level. (That is Master W immediately after a reset or the master which acquires the bus
mastership most recently in the low level when the fixed park master mode is not set, or Master W
that is the park master in the fixed park master mode.)
High Level
(Priority: High)
On-chip PCI Controller
Low Level
(Priority: Low)
[Workarounds]
There are two workarounds for this problem.
(1) Don't use the broken master function.
Don't set the BMCEN bit of the PBACFG register.
(2) When using the broken master function, use only the high level containing Master A, B, C and D.
Chapter 23 Notes on Use of TMPR4937
Master B
Master A
Low-level
Master
Master W
Master Z
Master Y
PCI Arbitration Priority
23-7
Request
Master C
Master D
Request
Master X
(Park master)
Broken Master
PCI Bus Master 1
Grant
Access is not started
within 16PCICLK
PCI Bus Master 2
PCI bus master 2
also becomes a
broken master.
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