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9.
SDRAM Controller
9.1
Characteristics
The SDRAM Controller (SDRAMC) generates the control signals required to interface with the SDRAM.
There are a total of four channels, which can each be operated independently. The SDRAM Controller
supports various bus configurations and a memory size of up to 2 GB.
The SDRAM has the following characteristics.
•
Memory clock (SDCLK) frequency: 50 − 133 MHz (For relationship between CPU clock and memory
•
Four independent memory channels
•
Can use registered DIMM
•
Selectable data bus width for each channel: 64-bit/32-bit
•
Supports critical word first access of the TX49/H3 core
•
Supports DMAC special Burst access (address decrement/fix)
•
Programmable SDRAM timing latency
Can set timing to match the clock frequency used and the memory speed. Can realize a system with
optimized memory performance.
•
Can write to any byte during Single or Burst Write operation. This feature is controlled by the DQM
signal.
•
Can set the refresh cycle to be programmable.
•
SDRAM refresh mode: both auto refresh and self refresh are possible.
•
Low power consumption mode: can select between self refresh or pre-charge power down
•
SDRAM Burst length: fixed to "2"
•
SDRAM addressing mode: Fixed to the Sequential mode
•
Supports systems with high fan-out
Supports two selectable data read-back buses and supports the Slow Write Burst Mode in order to
handle data buses with large load. In order to maintain timing consistency during Read operation, it is
possible to select whether to use the feedback clock to latch data or to by-pass this latch path. Two clock
cycles are used for each Write operation when in the Slow Write Burst Mode.
•
Can use the ECC or parity generation/check functions.
•
Can select EC (Error Check only), ECC (Error Check and Correct), or ECC + Scrub (write correction
data back to memory) when using the ECC function.
•
Can select Odd parity/Even parity when using the Parity function.
Chapter 9 SDRAM Controller
clock, see Section 6.1)
9-1
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