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Bit
Mnemonic
Field Name
Interrupt Source
19:18
IC25
Control 25
17:16
IC24
Interrupt Source
Control 24
15:14
IC15
Interrupt Source
Control 15
Interrupt Source
13:12
IC14
Control 14
11:10
IC13
Interrupt Source
Control 13
9:8
IC12
Interrupt Source
Control 12
7:6
IC11
Interrupt Source
Control 11
5:4
IC10
Interrupt Source
Control 10
Interrupt Source Control 25 (Default: 00, R/W)
These bits specify the active state of ACLCPME interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 24 (Default: 00, R/W)
These bits specify the active state of ACLC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 15 (Default: 00)
These bits specify the active state of PDMAC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 14 (Default: 00)
These bits specify the active state of IRC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 13 (Default: 00)
These bits specify the active state of DMA0 [3] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 12 (Default: 00)
These bits specify the active state of DMA0 [2] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 11 (Default: 00)
These bits specify the active state of DMA0 [1] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 10 (Default: 00)
These bits specify the active state of DMA0 [0] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Figure 15.4.3 Interrupt Detection Mode Register 1 (2/3)
15-15
Chapter 15 Interrupt Controller
Explanation
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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