Dma Destination Address Register (Dm0Darn, Dm1Darn) - Toshiba TX49 TMPR4937 Manual

8.4.5

DMA Destination Address Register (DM0DARn, DM1DARn)

Offset Address: DMAC0 0xB010 (ch. 0) / 0xB050 (ch. 1) / 0xB090 (ch. 2) / 0xB0D0 (ch. 3)
63
47
31
15
Bit Mnemonic Field Name
63:36 Reserved
35:0 DADDR Destination
Address
DMAC1 0xB810 (ch. 0) / 0xB850 (ch. 1) / 0xB890 (ch. 2) / 0xB8D0 (ch. 3)
Reserved
Reserved
DADDR[31:16]
R/W
⎯
DADDR[15:0]
R/W
⎯
Destination Address (Default: undefined)
This register sets the physical address of the transfer destination during
Dual Address transfer. This register is ignored during Single Address
transfer.
Refer to "8.3.8.1 Channel Register Settings During Dual Address Transfer"
for more information.
During Burst transfer, the value changes only by the size of data
transferred during each single bus operation. During Single transfer, the
value only changes by the value specified by the DMA Destination Address
Increment Register (DMDAIRn).
Figure 8.4.5 DMA Destination Address Register
8-34
Chapter 8 DMA Controller
36 35
DADDR[35:32]
Description
48
: Type
: Initial value
32
: Type
R/W
⎯ : Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W