Status Change Interrupt Status Register 0 (Siscisr0) 0Xf30C (Ch. 0) Status Change Interrupt Status Register 1 (Siscisr1) 0Xf40C (Ch. 1) - Toshiba TX49 TMPR4937 Manual

11.4.4 Status Change Interrupt Status Register 0 (SISCISR0)
Status Change Interrupt Status Register 1 (SISCISR1)
31
15
Bit Mnemonic Field Name
⎯
31:6 Reserved
5 OERS Overrun Error
4 CTSS CTS Status
3 RBRKD Receiving Break
2 TRDY Transmission
Data Empty
1 TXALS Transmission
Complete
0 UBRKD Break Detected
Reserved
Reserved
Overrun Error Status (Default: 0)
This bit is immediately set to "1" when an overrun error is detected. This bit
is cleared when a "0" is written.
CTS Terminal Status (Default: 0)
This field indicates the status of the CTS signal.
1: The CTS signal is High.
0: The CTS signal is Low.
Receive Break (Default: 0)
This bit is set when a break is detected. This bit is automatically cleared
when a frame that is not a break is received.
1: Current status is Break.
0: Current status is not Break.
Transmit Ready (Default: 1)
This bit is set to "1" if at least one stage in the Transmit FIFO is free.
Transmit All Sent (Default: 1)
This bit is set to "1" if the Transmit FIFO and all transmission shift registers
are empty.
UART Break Detect (Default: 0)
This bit is set when a break is detected. Once set, this bit remains set until
cleared by writing a "0" to it.
Figure 11.4.4 Status Change Interrupt Status Register
11-19
Chapter 11 Serial I/O Port
0xF30C (Ch. 0)
0xF40C (Ch. 1)
6 5 4 3 2
OERS CTSS TRDY TXALS
RBRKD
R/W0C R R R
0 0 0 1
Description
⎯
16
: Type
: Initial value
1 0
UBRKD
R R/W0C : Type
1 0 : Initial value
Read/Write
⎯
R/W0C
R
R
R
R
R/W0C