Toshiba TX49 TMPR4937 Manual page 98

Table 6.1.2 Relationship Among Different Clock Frequencies (for TMPR4937XBG-300, CPUCLK = 266 MHz)
Master Clock (Input)
Internal Clock
and Boot Configured
Settings
Boot
Configured
MASTERCLK CPUCLK
Setting
(MHz) (MHz)
ADDR[3:0]
133
HHHH (×2.0)
33.3
HLHH (×8.0)
106.4
HHHL (×2.5)
26.6
HLHL (×10.0)
88.7
HHLH (×3.0)
266
22.2
HLLH (×12.0)
66.5
HHLL (×4.0)
16.6
HLLL (×16.0)
59.1
LHHH (×4.5)
14.8
LLHH (×18.0)
† The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10].
Table 6.1.3 Relationship Among Different Clock Frequencies (for TMPR4937XBG-300, CPUCLK = 300 MHz)
Master Clock (Input)
Internal Clock
and Boot Configured
Settings
Boot
Configured
MASTERCLK CPUCLK
Setting
(MHz) (MHz)
ADDR[3:0]
-
HHHH(x2.0)
-
HLHH(x8.0)
120
HHHL (x2.5)
30
HLHL (x10.0)
100
HHLH (x3.0)
300
25
HLLH (x12.0)
75
HHLL (x4.0)
18
HLLL (x16.0)
66
LHHH(x4.5)
16
LLHH (x18.0)
† The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10].
SDCLK
Boot Configured Settings
GBUSCLK IMBUSCLK
[3:0]
(MHz) (MHz) (MHz)
HH
(1/1)
133 66 133 133
106.4 53 106.4 106.4
88.7 44 88.7 88.7
66.5 33.2 66.5 66.5
59.1 29.6 59.1 59.1
SYSCLK (MHz)
SDCLK
Boot Configured Settings
GBUSCLK IMBUSCLK
[3:0]
(MHz) (MHz) (MHz)
HH
(1/1)
- - - -
120 60 120 120
100 50 100 100
75 37 75 75
66 33 66 66
Chapter 6 Clocks
External Clock (Output)
SYSCLK (MHz)
PCIDIVMODE[2:0]
HL LH LL LLH LHH
(1/2) (1/3) (1/4) (1/4) (1/4.5)
66 44.3 33.3
53 35.5 26.6
66.5 59.1
44.3 29.6 22.2
33.3 22.2 16.6
29.6 19.7 14.8
External Clock (Output)
PCIDIVMODE[2:0]
HL LH LL LLH LHH
(1/2) (1/3) (1/4) (1/4) (1/4.5)
- - - - -
60 40 30
50 33 25
75 66
37 25 18
33 22 16
6-4
PCICLK[5:0] (MHz) †
CCFG Settings
PCIDIVMODE[2:0]
HLH HHH LLL LHL HLL
(1/5) (1/5.5) (1/8) (1/9) (1/10)
53.2 48.4 33.3 29.6 26.6 24.2
PCICLK[5:0] (MHz) †
CCFG Settings
PCIDIVMODE[2:0]
HLH HHH LLL LHL HLL
(1/5) (1/5.5) (1/8) (1/9) (1/10)
- - - - -
60 54 37 33 30
HHL
(1/11)
HHL
(1/11)
-
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