Toshiba TX49 TMPR4937 Manual page 123

Bit Mnemonic Field Name
Ready Input
6 RDY
Mode
5:4 SP Bus Speed
3 ME Master Enable
2:0 SHWT Set Up/Hold
Wait Time
Figure 7.4.1 External Bus Channel Control Register (3/3)
Chapter 7 External Bus Controller
Description
External Bus Control Ready Input Mode (Default: 0)
Specifies whether to use the Ready mode.
0: Disable the Ready mode.
1: Enable the Ready mode.
Note: The Ready mode cannot be used when the Page mode is selected.
External Bus Control Bus Speed (Default: ADDR[7:6] / 00)
Specifies the External Bus speed.
00: 1/4 speed (1/4 of the GBUSCLK frequency)
01: 1/3 speed (1/3 of the GBUSCLK frequency)
10: 1/2 speed (1/2 of the GBUSCLK frequency)
11: Full speed (same frequency as GBUSCLK)
Note: ADDR[7:6] is set to Channel 0 as the default.
External Bus Control Master Enable (Default: ADDR[8] / 0)
Enables a channel.
0: Disable channel
1: Enable channel
Note: ADDR[8] is set to Channel 0 as the default.
External Bus Control Setup/Hold Wait Time (Default: 000)
Specifies the wait count when switching between the Address and Chip
Enable signal, or the Chip Enable Signal and Write Enable/Output Enable
signal.
* 000: Disable 100: 4 wait cycles
001: 1wait cycle 101: 5 wait cycles
010: 2 wait cycles 110: 6 wait cycles
011: 3 wait cycles 111: 7 wait cycles
* Set this bit field to "0" when using it in the Page mode or when performing
Burst access.
7-23
Read/Write
R/W
R/W
R/W
R/W