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10.3.11.2 PDMAC Interrupts
Name
Normal Chain Termination
Normal Data Transfer Termination
Inter-Transfer Stall Time Reached
Configuration Error
PCI Fatal Error
G-Bus Chain Error
G-Bus Data Error
10.3.11.3 Power Management Interrupts
Name
PM Status Change Detect
PME_En Set Detect
PME Status Clear Detect
PME Detect
10.3.11.4 Error Detection Interrupts
Name
Parity Error Detect
System Error Report
Master Abort Receive
Target Abort Receive
Target Abort Report
Master Data Parity Error
TRDY Timeout Error
Retry Timeout Error
Broken Master Detect
Long Burst Transfer Detect
Negative Increase Burst Transfer Detect
Zero Increase Burst Transfer Detect
PERR* Detect
SERR* Detect
G-Bus Bus Error Detect
Note: In the initiator write cycle, access on the G-Bus has been finished before access on the PCI
bus is finished (Post write). Therefore, when an error occurs on PCI bus, it is reported with an
error detection interrupt, as shown above.
In the initiator read cycle, when an error occurs on the PCI bus access, PCIC responds with a
G-Bus error instead of returning read data to the G-Bus. Setting "0" to the IRBER bit of the
PCICFG register suppresses output of a G-Bus error during initiator read.
Chapter 10 PCI Controller
Status Bit
NCCMP
NTCMP
STLTRF
PDMSTATUS
CFGERR
PCIERR
CHNERR
DATAERR
Status Bit
PMSC
P2GSTATUS
PMEES
PMECLR
PCICSTATUS
PME
Status Bit
DPE
SSE
RMA
PCISTATUS
/ PCISSTATUS
RTA
STA
MDPE
IDTTOE
G2PSTATUS
IDRTOE
PBASTATUS
BMD
TLB
NIB
ZIB
PCICSTATUS
PERR
SERR
GBE
10-19
Interrupt Enable Bit
NCCMPIE
NTCMPIE
PDMCFG
ERRIE
Interrupt Enable Bit
PMSCIE
P2GMASK
PMEESIE
PMECLRIE
PCICMASK
PMEIE
Interrupt Enable Bit
DPEIE
SSEIE
RMAIE
PCIMASK
RTAIE
STAIE
MDPEIE
IDTTOEIE
G2PMASK
IDRTOEIE
PBAMASK
BMDIE
TLBIE
NIBIE
ZIBIE
PCICMASK
PERRIE
SERRIE
GBEIE
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