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3.1.6
Serial I/O Interface Signals
Signal Name
Type
CTS [1:0]*
Input
SIO Clear to Send
PU
CTS* signals.
RTS [1:0]*
Output
SIO Request to Send
RTS* signals.
RXD[1:0]
Input
SIO Receive Data
PU
Serial data input signals.
TXD[1:0]
3-state
SIO Transmit Data
Output
Serial data output signals.
SCLK
Input
External Serial Clock
PU
SIO clock input signal. SIO0 and SIO1 share this signal.
3.1.7
Timer Interface Signals
Signal Name
Type
TIMER[1:0]
Output
Timer Output
Timer output signals.
TCLK
Input
External Timer Clock
PU
Timer input clock signal. TMR0, TMR1, and TMR2 share this signal.
WDRST*
OD output
Watchdog Reset
Watchdog reset output signal.
3.1.8
Parallel I/O Interface Signals
Signal Name
Type
PIO[15:8]
Input/output
PIO Ports[15:8]
PU
Parallel I/O signals.
PIO[15:8] share pins with the SDRAM ECC/parity signals (CB[7:0]). The boot
configuration signal on the ADDR[18] pin selects between PIO[5:8] and CB[7:0] (refer to
Section "3.3 Pin multiplex").
PIO[7:0]
Input/output
PIO Ports[7:0]
PU
Parallel I/O signals.
PIO[4:2] share pins with the AC-link interface signals (SDOUT, SDIN[0], and BITCLK).
The boot configuration signal on the ADDR[9] pin selects between PIO[4:2] and AC-link
interface signals (refer to Section "3.3 Pin multiplex").
Table 3.1.6 Serial I/O Interface Signals
Description
Table 3.1.7 Timer Interface Signals
Description
Table 3.1.8 Parallel I/O Interface Signals
Description
3-6
Chapter 3 Signals
Initial State
Input
All Low
Input
All High
Input
Initial State
All High
Input
Hi-Z
Initial State
Input
Input
(other than
PIO[4])
Selected by
ADDR[9]
(PIO[4] only)
L: Input
H: All Low
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