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21.5.7
PCI EEPROM Interface AC characteristics
Item
EEPROM_SK High Time
EEPROM_SK Low Time
EEPROM_DO Output Delay Time
EEPROM_DI Input Setup Time
EEPROM_DI Input Hold Time
EEPROM_CS Output Delay Time
*1) The TX4937 controls EEPROM and its control signal synchronous to the falling edge of
EEPROM_SK. Since the EEPROM operates at the rising edge of EEPROM_SK, you do not have
to take the MIN side of EEPROM_DO into account.
EEPROM_SK
EEPROM_DO
EEPROM_DI
EEPROM_CS
Figure 21.5.8 Timing Diagram: PCI EEPROM Interface
21.5.8
DMA Interface AC characteristics
Item
DMADONE * Delay
DMADONE * Input Pulse Width Time
DMADONE *
SYSCLK
DMADONE *
(Tc = 0 ~ 70°C, V
CCIO
Symbol
t
C
=50 pF
HIGH_EPSK
L
t
C
=50 pF
LOW_EPSK
L
* 1)
t
C
=50 pF
VAL_EPDO
L
t
SU_EPDI
t
HO_EPDI
t
C
=50 pF
VAL_CS
L
t
HIGH_EPSK
t
SU_EPDI
t
VAL_EPCS
(Tc = 0 – 70°C, V
CCIO
Symbol
Conditions
t
C
=50 pF
VAL_DONE
L
SYSCLK (C
L
t
Boot configuration
PW_DONE
ADDR[2]=H
Boot configuration
ADDR[2]=L
t
PW_DONE
t
VAL_DONE
Figure 21.5.9 Timing Diagram: DMA Interface
21-11
Chapter 21 Electrical Characteristics
= 3.3 V ± 0.2 V, V
= 1.5 V ± 0.1 V, V
CCInt
Conditions
Min.
500
500
⎯
100
100
100
t
LOW_EPSK
t
VAL_EPDO
t
HO_EPDI
= 3.3 V ± 0.2 V, V
= 1.5 V ± 0.1 V, V
CCInt
Min.
⎯
=50 pF) reference
× 1.1
t
MCP
1/4 × t
MCP
= 0 V)
SS
Max.
Unit
⎯
ns
⎯
ns
100
ns
⎯
ns
⎯
ns
⎯
ns
= 0 V)
SS
Max.
Unit
12
ns
⎯
ns
× 1.1
⎯
ns
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