Table of Contents
Advertisement
14.3.6.5 Sample-data FIFO
For a transmission stream, as long as ACLC Control Enable Register (ACCTLEN) allows that
transmission and the FIFO has any room to fill data in, the FIFO issues a request via the REQ
latch. On the other side, when a transmission FIFO receives a data-request from the link-side, it
provides data with valid-flag set if it has any valid data. If it has no valid data, it responds with
valid-flag unset and an underrun error bit is set.
At the transmit-data DMA start-up, until the FIFO becomes full, it responds to the link-side
with valid-flag unset, in order to maximize the buffering effect. Therefore, the DMA size must be
the FIFO depth or more.
Table 14.3.8 Transmission FIFO Depth
PCM L&R out
Surround L&R out
Center out
LFE out
Modem Line 1 out
The link-side drives the slot-valid bit and slot-data on AC-link. When underrun occurs, these
bits are driven to all '0'.
For a reception stream, as long as the FIFO has any valid data, the FIFO issues a request via the
REQ latch. On the other side, when ACCTLEN allows that reception and the link-side issues a
data strobe, the FIFO stores the valid data. If the FIFO is full when it receives a data strobe, the
data is discarded and an overrun error bit is set.
14.3.6.6 Error Detection and Recovery
In most usages, since the CODEC continuously requests sample-data transmission and
reception, after DMA is finished, underrun and overrun will occur. The procedure described
below allows the software to determine whether an error has occurred during DMA operation.
The software sets ACLC Control Enable Register (ACCTLEN)'s Error Halt Enable
(xxxxEHLT) bit before it starts a DMA channel. After it starts the DMA channel, it waits until
ACLC Interrupt Status Register (ACINTSTS)'s Underrun or Overrun Error (xxxxERR) bit is set.
When the event is detected, the software checks DMA Channel Control Register (DMCCRn)'s
Transfer Active (XFACT) bit and ACLC DMA Request Status Register (ACDMASTS)'s Request
(xxxxDMA) bit and determines the DMA completion status as follows.
Table 14.3.9 DMA Completion Status Determination
DMCCRn.XFACT
Inactive
Inactive
Active
To recover from error, disable and enable the stream via ACCTLEN, and restart the DMA.
Data-stream
FIFO Depth (Word)
ACDMASTS.xxxxDMA
Pending
Not Pending
*
14-13
Chapter 14 AC-link Controller
3
3
2
2
1
Completion Status
No Error during DMA
Underrun or Overrun
Underrun or Overrun
Advertisement
Table of Contents
