Pci Bus Arbiter Interrupt Mask Register (Pbamask) 0Xd10C - Toshiba TX49 TMPR4937 Manual

10.4.26 PCI Bus Arbiter Interrupt Mask Register (PBAMASK)
This register is only valid when using the on-chip PCI Bus Arbiter.
31
15
Bit Mnemonic Field Name
31:1 Reserved
0 BMIE Broken Master
Detected Interrupt
Enable
Reserved
Reserved
Broken Master Detected Interrupt Enable (Default: 0)
Generates an interrupt when a Broken Master is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
Figure 10.4.24 PCI Bus Arbiter Interrupt Mask Register
10-53
Chapter 10 PCI Controller
0xD10C
Description
16
: Type
: Initial value
1 0
BMIE
R/W : Type
0 : Initial value
Read/Write
⎯
R/W