Toshiba TX49 TMPR4937 Manual page 427

Bit Mnemonic Field Name
13 Reserved
12 —
11 —
10 —
9 —
8 —
7:5 Reserved
4 —
3 —
2 —
1 —
0 —
Clear xxxxDMA bits in ACCTLEN to "0" by using this register to disable transmit/receive-data
DMA and to stop transmission/reception by the AC-link. Note that if these bits are cleared while
output-slot data is flowing in the FIFO, ACLC may output a wrong data as the last sample. This
behavior will not occur if the software waits for data-flow completion by detecting underrun before it
disables the corresponding slot.
Description
AUDIDMA: Disable Audio Receive-data DMA.
W1C 0: No effect
1: Disables audio receive-data DMA.
LFEDMA: Disable Audio LFE Transmit-data DMA.
W1C 0: No effect
1: Disables audio LFE transmit-data DMA.
CENTDMA: Disable Audio Center Transmit-data DMA.
W1C 0: No effect
1: Disables audio Center transmit-data DMA.
SURRDMA: Disable Audio Surround L&R Transmit-data DMA.
W1C 0: No effect
1: Disables audio Surround L&R transmit-data DMA.
AUDODMA: Disable Audio PCM L&R Transmit-data DMA.
W1C 0: No effect
1: Disables audio PCM L&R transmit-data DMA.
MICSEL: MIC Selection
W1C 0: No effect
1: Selects PCM L&R (Slot 3&4) for audio reception
WRESET: Deassert Warm Reset.
W1C 0: No effect
1: Deasserts warm reset.
[Note: The software must guarantee the warm reset assertion
time meets the AC'97 specification (1.0 µs or more).]
WAKEUP: Disable Wake-up.
W1C 0: No effect
1: Disables wake-up from low-power mode.
LOWPWR: Disable AC-link Low-power Mode.
W1C 0: No effect
1: Releases SYNC and SDOUT signals from low.
ENLINK: Disable AC-link.
W1C 0: No effect
1: Asserts the ACRESET* signal to AC-link.
[Note: The software must guarantee the ACRESET* signal
assertion time meets the AC'97 specification (1.0 µs or
more).]
Figure 14.4.2 ACCTLDIS Register (2/2)
14-21
Chapter 14 AC-link Controller
Read/Write
⎯
W1C
W1C
W1C
W1C
W1C
⎯
W1C
W1C
W1C
W1C
W1C