Toshiba TX49 TMPR4937 Manual page 378

Bit Mnemonic Field Name
7 RDIS Reception Data
Full
6 STIS Status Change
5 Reserved
4:0 RFDN Reception Data
Stage Status
Receive DMA/Interrupt Status (Default: 0)
This bit is set when valid data of the amount set by the Receive FIFO
Request Trigger Level (RDIL) of the FIFO Control register (SIFCR) is stored
in the Receive FIFO.
Status Change Interrupt Status (Default: 0)
This bit is set when at least one of the interrupt statuses selected by the
Status Change Interrupt Condition field (STIE) of the DMA/Interrupt Control
Register (SIDICR) becomes "1".
Receive FIFO Data Number (Default: 00000)
This field indicates how many stages of reception data remain in the
Receive FIFO
(0 – 16 stages).
Figure 11.4.3 DMA/Interrupt Status Register (2/2)
11-18
Chapter 11 Serial I/O Port
Description Read/Write
R/W0C
R/W0C
⎯
R