Sample-Data Transmission And Reception - Toshiba TX49 TMPR4937 Manual

14.3.6

Sample-data Transmission and Reception

This section describes the mechanism for transmission and reception of PCM audio and modem
wave-data. An overview is described first.
detection and recovery procedure follow. A special case using slot activation control is described last.
14.3.6.1 Overview
Figure 14.3.6 and Figure 14.3.7 show conceptual views of the sample-data transmission and
reception mechanisms.
Memory DMAC
Read
DMA
Data
Buffer
Figure 14.3.6 Sample-data Transmission Mechanism
Memory DMAC
Write
DMA
Data
Buffer
Figure 14.3.7 Sample-data Reception Mechanism
The CODEC requests ACLC to transmit and receive sample-data via 'slot-request' and 'slot-
valid' bit-fields on the SDIN signal of AC-link.
For transmission, ACLC transmits the data with 'slot-valid' tag set. For reception, ACLC
captures the slot-data.
Transmission or reception through each stream can be independently activated or deactivated
under control of ACLC Slot Enable Register (ACSLTEN).
ACLC is equipped with a separate FIFO for each data-stream.
prefetched from memory to FIFO through DMA. The received data is buffered on FIFO and then
stored to memory through DMA.
deactivated under control of ACLC Control Enable Register (ACCTLEN).
The DMA (Direct Memory Access) operation, error
REQ
ACCTLEN
Latch
DMAREQ
Strobe
Write
Data
REQ
ACCTLEN
Latch
DMAREQ
Strobe
Read
Data
In this stage, each DMA is independently activated or
14-9
Chapter 14 AC-link Controller
ACLC
Link-
ACSLTEN
FIFO
side
Valid Flag
Data
Underrun Error
ACLC
Link-
ACSLTEN
FIFO
side
Data
Overrun Error
The data to transmit is
AC-link
Slot Req
Slot Valid,
Slot Data
AC-link
Slot Valid,
Slot Data