Interrupt Detection Mode Register 0 (Irdm0) 0Xf604 - Toshiba TX49 TMPR4937 Manual

15.4.2 Interrupt Detection Mode Register 0 (IRDM0)
31 30 29
IC23 IC22
R/W R/W
0 0
15 14 13
IC7 IC6
R/W R/W
0 0
Bits Mnemonic Field Name
31:30 IC23 Interrupt Source
Control 23
29:28 IC22 Interrupt Source
Control 22
27:26 IC21 Interrupt Source
Control 21
⎯
25:24
23:22 IC19 Interrupt Source
Control 19
Interrupt Source
21:20 IC18
Control 18
19:18 IC17 Interrupt Source
Control 17
28 27 24
IC21 Reserved
R/W
0
12 11 10 9 8
IC5 IC4
R/W R/W
0 0
Interrupt Source Control 23 (Default: 00)
These bits specify the active state of PCIPMC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 22 (Default: 00)
These bits specify the active state of PCIERR0 interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 21 (Default: 00)
These bits specify the active state of NDFMC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
⎯
Reserved
Interrupt Source Control 19 (Default: 00)
These bits specify the active state of TMR[2] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 18 (Default: 00)
These bits specify the active state of TMR[1] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Interrupt Source Control 17 (Default: 00)
These bits specify the active state of TMR[0] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
Figure 15.4.2 Interrupt Detection Mode Register 0 (1/2)
Chapter 15 Interrupt Controller
0xF604
23 22 21 20
IC19 IC18
R/W R/W
0 0
7 6 5 4
IC3 IC2
R/W R/W
0 0
Explanation
15-12
19 18 17 16
IC17 IC16
R/W R/W : Type
0 0 : Default
3 2 1 0
IC1 IC0
R/W R/W : Type
0 0 : Default
Read/Write
R/W
R/W
R/W
⎯
R/W
R/W
R/W