Ecc - Toshiba TX49 TMPR4937 Manual

9.3.10

ECC

9.3.10.1 ECC/Parity Mode
Table 9.3.5 shows the supported ECC/Parity functions. The ECC/Parity mode can be set
separately for each channel using the ECC/Parity Mode field (SDCCRn.ECC) of the SDRAM
Channel Control Register. The ECC enable bit (ECCCR.ECCE) of the ECC Control Register must
be set in order to use the ECC function. No error detection, logging, or notification will be
performed if this bit is not set.
ECC Field Mode Name
0x0 NOP Mode
0x1 EC Mode
0x2 ECC Mode
0x3 ECC + Scrub Mode
0x4 Even Parity Mode
0x5 Odd Parity Mode
0x6 —
0x7 —
•
The ECC/Parity Mode changes dynamically according to each channel setting.
•
Error checking is performed when writing data smaller than 64 bits when Memory Read
access is being performed while in the EC Mode, ECC Mode, or ECC + scrub mode.
•
Data correction is performed if the read data cause a single-bit error when in the ECC Mode
or the ECC + scrub mode. Data is read unchanged when in any other mode regardless of
whether or not an error occurs.
Chapter 9 SDRAM Controller
Table 9.3.5 ECC/Parity Mode
Disables the ECC/Parity function.
EC (Error Check) enable
Read: Performs only error checking. Correction is not performed.
Write: Generates check code.
ECC (Error Check and Correct) enable
Read: Performs error checking and correction.
Write: Generates check code.
ECC + scrub enable
Read: Performs error checking and correction. Corrected data is written back to
memory if an error occurs.
Write: Generates check code.
Even parity enable
Read: Performs error checking.
Write: Generates even parity.
Odd parity enable
Read: Performs error checking.
Write: Generates odd parity.
Reserved
Reserved
9-13
Description