Table of Contents
Advertisement
•
When edge detection is set (DMCCRn.EGREQ = 1)
Please set up assertion of the DMAREQ[n] signal so the DMAREQ[n] signal is asserted
after the DMAACK[n] signal corresponding to a previously asserted DMAREQ[n] signal is
deasserted. The DMAREQ[n] signal will not be detected even if it is asserted before
DMAACK[n] is deasserted.
Figure 8.3.1 is a timing diagram that shows the timing of external DMA access. In this timing
diagram, both the DMAREQ[n] signal and the DMAACK[n] signal are set to Low active
(DMCCRn.REQPL = 0, DMCCRn.ACKPOL = 0).
The DMAACK[n] and DMADONE[n] signals, which are DMA control signals, are
synchronized to SDCLK. When these signals are used by an external I/O device that is
synchronous to SYSCLK, it is necessary to take clock skew into account.
The DMAACK[n] signal is asserted either at the SYSCLK cycle, the same as with assertion of
the CE*/CS* signal, or before that. In addition, it is deasserted after the last ACK*/READY signal
is deasserted.
When the DMADONE* signal (refer to 8.3.3.4) is used as an output signal, it is asserted for at
least one SYSCLK cycle while the DMAACK[n] signal is asserted either during the same
SYSCLK cycle that the CE*/CS* signal is deasserted or during a subsequent SYSCLK cycle.
When the DMADONE* signal is used as an input signal, it must be asserted for one SYSCLK
cycle while the DMAACK[n] signal is being asserted.
SYSCLK
CE*
ADDR [19:0]
ACE*
OE*/BUSSPRT*
SWE*
BWE*
DATA [31:0]
ACK*
1 cycle
DMAREQ[n]
DMAACK[n]
DMADONE*
Figure 8.3.1 External I/O DMA Transfer (Single Address, Level Request)
1c040
f
8-6
Chapter 8 DMA Controller
00040
00000100
Advertisement
Table of Contents
