Toshiba TX49 TMPR4937 Manual page 188

Bit Mnemonic Field Name
8 XFACT Transfer Active
7 ABCHC Error Complete
6 NCHNC Chain Complete
5 NTRNFC Transfer
Complete
External DONE
4 EXTDN
Asserted
3 CFERR Configuration
Error
2 CHERR Chain Bus Error
1 DESERR Destination Error
0 SORERR Source Bus Error
Transfer Active (Default: 0)
This value is a copy of the Transfer Active bit (XFACT) of the DMA
Channel Control Register (DMCCRn).
Error Completion (Default: 0)
This bit indicates whether an error occurred during DMA transfer. This bit
indicates the logical sum of the four error bits (CFERR, CHERR, DESERR,
SORERR) in DMCSRn[3:0].
1: DMA transfer ends due to an error.
0: No error occurred since this bit was last cleared.
Normal Chain Completion (Default: 0)
When performing chain DMA transfer, This bit indicates whether all DMA
data transfers in the DMA Descriptor chain are complete.
1: All DMA data transfers in the DMA Descriptor chain ended normally. Or,
DMA transfer that did not use a DMA Descriptor chain ended normally.
0: DMA transfer has not ended normally since this bit was last cleared.
Normal Transfer Completion (Default: 0)
This bit indicates whether DMA transfer ended according to the current
DMA Channel Register setting.
1: DMA transfer ended normally.
0: DMA transfer has not ended since this bit was last cleared.
External Done Asserted (Default: 0)
This bit indicates whether an external I/O device asserted the DMADONE*
signal. When the DMADONE* signal is set to bidirectional, this bit is also
set when the TX4937 asserts the DMADONE* signal.
1: DMADONE* signal was asserted.
0: DMADONE* signal was not asserted.
Configuration Error (Default: 0)
Indicates whether an illegal register setting was made.
1: There was a configuration error.
0: There was no configuration error.
Chain Bus Error (Default: 0)
This bit indicates whether a bus error occurred while reading a DMA
Command Descriptor.
1: Bus error occurred.
0: No bus error occurred.
Destination Bus Error (Default: 0)
This bit indicates whether a bus error occurred during a destination bus
Write operation (a Write to a set DMDARn address).
1: Bus error occurred.
0: No bus error occurred.
Source Bus Error (Default: 0)
This bit indicates whether a bus error occurred during either a source bus
Read or Write operation (A Read or Write to a set DMSARn address).
1: Bus error occurred.
0: No bus error occurred.
Figure 8.4.3 DMA Channel Status Register (2/2)
8-32
Chapter 8 DMA Controller
Description Read/Write
R
R
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C