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Bus errors occur the following three conditions.
(1) When CCFG.TOE of the Chip Configuration Register is set to "1" (Default: 0), G-Bus timeout
error detection is enabled, and the following situation results:
•
A Bus timeout occurs when a G-Bus Bus Master (TX49/H3 Core, DMAC, or PCIC) is reading
the G-Bus
•
A Bus timeout occurs when a G-Bus Bus Master (other than the TX49/H3 Core) is writing to
the G-Bus
(2) When ECCCR.MEB of the ECCCR Register in the SDRAM Controller is set to "1" (Default: 0),
Parity errors are enabled during a multi-bit error, and the following situation results:
•
A 2-bit ECC error or Parity error is detected during SDRAM Read operation by the TX49/H3
Core
•
A 2-bit ECC error or Parity error is detected during Read/Write operation by a G-Bus Bus
Master other than the TX49/H3 Core
(3) When PCICCFG.IRBER of the PCICCFG Register in the PCI Controller is set to "1" (Default: 1),
and the following situation results during initiator Read operation:
•
A Parity error is detected
•
A Master ABORT is received
•
A Target ABORT is received
•
A TRDY timeout is detected
•
A Retry timeout is detected
There is no problem for ColdReset or SoftReset exceptions because initialization processing is
performed after the exception occurs. Also, there is no problem for NMI exceptions if the process after
the exception occurs is similar to the above reset process.
[Workaround]
•
There is no problem if error notification to the TX49/H3 Core using Bus errors is not enabled
in the above Conditions.
•
Executing a SYNC instruction immediately after the preceding load instruction allows you to
avoid condition because the next instruction will not be executed until the Load data arrives.
Chapter 23 Notes on Use of TMPR4937
23-2
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