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Rev 1.1 Manual
Figure 11.4.7 Baud Rate Control Register
Modified the description of the BCLK (Baud Rate Generator
Clock) field.
11-22
00: Select prescalar output T0 (IMBUSCLK/2)
01: Select prescalar output T2 (IMBUSCLK/8)
10: Select prescalar output T4 (IMBUSCLK/32)
11: Select prescalar output T6 (IMBUSCLK/128)
12-10
Table 14.3.7 Mic DMA Buffer Format in Big-endian Mode
Address offset
z
14-11
+4
+8
:
Modified line 3 of Section 15.3.1, Interrupt sources
15-5
Please refer to the 64-bit TX System RISC TX49/H3 Core
Architecture Manual for more information.
Modified line 2 of Section 20.2.1, JTAG Controller and
Register
20-2
Please refer to the TX49/H3 Core Architecture Manual for
all other portion not covered here.
Modified line 3 of 20.2.2, Instruction Register
20-3
Refer to the TX49/H3 Core Architecture Manual for more
information regarding each instruction.
Table 20.2.1 Bit Configuration of JTAG Instruction Register
20-3
Refer to the TX49/H3 Core Architecture Manual
Modified line 5 of Section 20.3, Initializing the Extended
EJTAG Interface
20-7
(Hold the signal low for 2 or more clock cycles of the TCK
input.)
After that, deassert the TRST* signal High.
00: Select prescalar output T0 (fc/2)
01: Select prescalar output T2 (fc/8)
10: Select prescalar output T4 (fc/32)
11: Select prescalar output T6 (fc/128)
Figure 12.4.1 Timer Control Register
Added the following text to the description of the Counter
Reset Enable field
During CRE = 1, reset the counter if TCE is set from 1 to 0.
During TCE = 0, the counter isn't reset if CRE is set from 0
to 1.
When TCE = 1 and CRE = 0, stop and reset the counter if
TCE is set to 0 and CRE is set to 1 simultaneously.
+0
+1
#0
#0
H
L
#1
#1
H
L
#2
#2
H
L
:
:
Please refer to the
TX49/H3, TX49/H4 Core Architecture"
Please refer to the
TX49/H3, TX49/H4 Core Architecture"
not covered here.
Refer to the
TX49/H4 Core Architecture"
each instruction.
Refer to the
TX49/H4 Core Architecture"
(TRST * signal is pulled down (by ex. 10 k Ω ))
6
TMPR4937 Revision History
Changes and Additions to Rev 1.1
Address offset
+0
+0
#0
H
+4
#1
H
+8
#2
H
:
:
"64-bit TX System RISC TX49/H2,
"64-bit TX System RISC TX49/H2,
"64-bit TX System RISC TX49/H2, TX49/H3,
for more information regarding
"64-bit TX System RISC TX49/H2, TX49/H3,
+1
#0
L
#1
L
#2
L
:
for more information.
for all other portion
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