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15.4.4
Interrupt Level Register 0 (IRLVL0)
31
Reserved
15
Reserved
Bit
Mnemonic
Field Name
⎯
31:27
26:24
IL17
Interrupt Level 17
⎯
23:19
18:16
IL16
Interrupt Level 16
⎯
15:11
10:8
IL1
Interrupt Level 1
⎯
7:3
27
26
24
IL17
R/W
000
11
10
8
IL1
R/W
000
⎯
Reserved
Interrupt Level of INT [17] (Default: 000)
These bits specify the interrupt level of [TMR [0]
000: Interrupt Level 0 (Interrupt disable)
001:Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Interrupt Level of INT [16] (Default: 000)
These bits specify the interrupt level of PCIC0 interrupts.
000: Interrupt level 0 (Interrupt disable)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Interrupt Level of INT [1] (Default: 000)
These bits specify the interrupt level for TX49 Write Timeout Error
interrupts.
000: Interrupt level 0 (Interrupt disable)
001: Interrupt level 1
010:Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Figure 15.4.4 Interrupt Level Register 0 (1/2)
15-17
Chapter 15 Interrupt Controller
0xF610
23
19
Reserved
7
3
Reserved
Explanation
18
16
IL16
R/W
: Type
000
: Default
2
0
IL0
R/W
: Type
000
: Default
Read/Write
⎯
R/W
⎯
R/W
⎯
R/W
⎯
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