Access Mode - Toshiba TX49 TMPR4937 Manual

7.3.6

Access Mode

The following four modes are available as controller access modes. These modes can be set
separately for each channel.
•
Normal mode
•
Page mode
•
External ACK mode
•
Ready mode
Depending on the combination of modes in each channel, either of two modes in which the
ACK*/Ready signal operates differently (ACK*/Ready Dynamic mode, ACK*/Ready Static mode) is
selected by the ACK*/Ready Mode bit (CCFG.ARMODE) of the Chip Configuration Register. The
mode selected is applied globally to all channels.
(1) ACK*/READY Dynamic mode (CCFG.ARMODE = 0)
This mode is selected in the initial state.
The ACK*/Ready signal automatically switches to either input or output according to the setting of
each channel. When in the Normal mode or the Page mode, the ACK*/Ready signal is an output
signal, and the internally generated ACK* signal is output. When in the External ACK* or Ready
mode, the ACK*/Ready signal becomes an input signal. The ACK*/Ready signal outputs High if
there is no access to the External Bus Controller. However, this signal may output Low during
access to SDRAM.
Please refer to the timing diagrams (Figure 7.5.23 and Figure 7.5.24) and be careful to avoid
conflicts when switching from output to input.
(2) ACK*/Ready Static mode (CCFG.ARMODE = 0)
The internally generated ACK* signal is not output when in either the Normal mode or Page mode.
Therefore, the ACK*/Ready signal will not become an output in any channel.
Access using Burst transfer by the internal bus (G-Bus) is supported when in a mode other than the
Ready mode. However, the Ready mode is not supported.
PM RDY
0
ACK*/Ready
Dynamic Mode
!0
0
ACK*/Ready
Static Mode
!0
Table 7.3.7 Operation Mode
PWT:WT Mode
!3f Normal
0
3f External ACK*
⎯
1 READY
⎯
0 Page
⎯
1 Reserved
!3f Normal
0
3f External ACK*
⎯
1 READY
⎯
0 Page
⎯
1 Reserved
7-9
Chapter 7 External Bus Controller
ACK*/READY Access End
Timing State
Pin State
Internally
Output
Generated ACK*
Input ACK* Input
Input Ready Input
Internally
Output
Generated ACK*
⎯
Internally
Hi-Z
Generated ACK*
Input ACK* Input
Input Ready Input
Internally
Hi-Z
Generated ACK*
⎯
G-Bus Burst
Access
√
√
⎯
√
⎯ ⎯
√
√
⎯
√
⎯ ⎯