Toshiba TX49 TMPR4937 Manual page 376

Bit Mnemonic Field Name
Status Change
5:0 STIE
Interrupt Enable
Status Change Interrupt Enable (Default: 0x00)
This field sets the set conditions of the Status Change bit (STIS) of the
DMA/Interrupt Status Register (SIDISR). The condition is selected
depending on which bit of the Status Change Interrupt Status Register
(SISCISR) is set. (Multiple selections are possible.)
An SIO interrupt is asserted when STIC is "1".
000000: Do not detect status changes.
1*****: Set "1" to STIS when the Overrun bit (OERS) is "1".
*1****: Set "1" to STIS when a change occurs in a condition set by the
CTSS Active Condition field (CTSAC) in the CTS Status bit
(CTSS).
**1***: Set "1" to STIS when the Break bit (RBRKD) becomes "1".
***1**: Set "1" to STIS when the Transmit Data Empty bit (TRDY)
becomes "1".
****1*: Set "1" to STIS when the Transmission Complete bit (TXALS)
becomes "1".
*****1: Set "1" to STIS when the Break Detection bit (UBRKD) becomes
"1".
Figure 11.4.2 DMA/Interrupt Control Register (2/2)
11-16
Chapter 11 Serial I/O Port
Description Read/Write
R/W