Toshiba TX49 TMPR4937 Manual page 546

Page Rev 1.1 Manual
Figure 5.2.1 Chip Configuration Register (1/3)
42
5-3
Figure 5.2.1 Chip Configuration Register (1/3)
17
5-3
Figure 5.2.1 Chip Configuration Register (1/3)
Read/write attribute of the WDRST (Watchdog Reset
5-3 Status) bit
RW1C
Figure 5.2.1 Chip Configuration Register (2/3)
Read/write attribute of the BEOW (Write-Access Bus Error)
5-4 bit
RW1C
Figure 5.2.3 Pin Configuration Register (1/3)
47 45
DRVCS
R/W
ADDR[5]
5-7
31 30 29
Reserved SDCLKDLY
R/W
00
Figure 5.2.3 Pin Configuration Register (1/3)
21
5-7
5-7
41 40
WDRST
WDREXEN
RW1C R/W
0 0
16
BEOW
RW1C : Type
0 : Initial value
44 41 40
DRVCK[3:0]
DRVCKIN
R/W R/W
ADDR[5]
ADDR[5]
28 27 26
SDCLKEN
SYSCLKEN
R/W R/W
1 1111
16
PCICLKEN
R/W
111111
2
TMPR4937 Revision History
Changes and Additions to Rev 1.1
42 41
WDRST
R/W1C
17 16
BEOW
R/W1C
0
R/W1C
R/W1C
3 47 45 44
DRVCS[2:0]
R/W
ADDR[5]
2 31 30 29 28
Reserved SDCLKDLY
SYSCLKEN
R/W
00
21
PCICLKEN[5:0]
R/W
111111
Figure 5.2.3 Pin Configuration Register (1/3)
Added a note to the description of the DRVCB (CB Signal
Control) bit
Note: CB[7:0]* share pins with PIO[15:8], E0TXD[3:0],
E0RXD[3:0].
The driving capability of these pins are below.
CB[7:0], E0TXD[3:0], E0RXD[3:0]: 8 mA or 16 mA
PIO[15:8]: 8 mA only
40
WDREXEN
R/W
0 0
: Type
: Initial value
41 40 3
DRVCK[3:0]
DRVCKIN
R/W R/W
ADDR[5]
ADDR[5]
27 26 2
SDCLKEN[3:0]
R/W R/W
1 1111
16