G-Bus Arbiter Control Register (Garbc) 0Xe030 - Toshiba TX49 TMPR4937 Manual

5.2.6 G-Bus Arbiter Control Register (GARBC)
63
47
31 30
ARBMD
R/W
1
15 14
Reserved
Bit Mnemonic Field Name
⎯
63:32 Reserved
Arbitration
31 ARBMD
Mode
⎯
30:15 Reserved
14:0 PRIORITY Arbitration
Priority
Reserved
Reserved
Reserved
PRIORITY
R/W
000_001_010_011_100
Description
Specifies how to prioritize G-Bus arbitration.
0 = Fixed priority. The G-Bus arbitration priority conforms to
the content of the PRIORITY field (bits [14:0]).
1 = Round-robin (in a round-robin fashion, PCIC0 > PDMAC >
DMAC0 > DMAC1 > PCIC1)
Note: Before accessing the PCI by DMAC, specify round-robin
as the priority mode. If fixed-priority mode is selected, a
dead lock is likely to occur in PCI bus access.
Specifies the priority when ARBMD (bit [16]) specifies fixed-
priority mode.
[14:12] = Bus master with the highest priority
[11:9] = Bus master with the second highest priority
[8:6] = Bus master with the third highest priority
[5:3] = Bus master with the fourth highest priority
[2:0] = Reserved (Please do not rewrite.)
000 = PCI controller
001 = PDMAC
010 = DMAC0
011 = DMAC1
A priority of PCIC > PDMAC > DMAC0 > DMAC1 is initially set
up.
Figure 5.2.6 G-Bus Arbiter Control Register
5-13
Chapter 5 Configuration Registers
0xE030
⎯
⎯
48
: Type
: Initial value
32
: Type
: Initial value
16
: Type
: Initial value
0
: Type
: Initial value
Initial Value Read/Write
⎯ ⎯
1 R/W
⎯ ⎯
000_001_01 R/W
0_011_100