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3.1.9
AC-link Interface Signals
Signal Name
Type
ACRESET*
Output
AC '97 Master H/W Reset
ACRESET* shares the pin with the DMAREQ[2] signal. The boot configuration signal on
the ADDR[9] pin selects between ACRESET* and DMAREQ[2] (refer to Section "3.3 Pin
multiplex").
SYNC
Output
48 kHz Fixed Rate Sample Sync
SYNC shares the pin with the DMAACK[2] signal. The boot configuration signal on the
ADDR[9] pin selects between SYNC and DMAACK[2] (refer to Section "3.3 Pin
multiplex").
SDOUT
Output
Serial, Time Division Multiplexed, AC '97 Output Stream
SDOUT shares the pin with the PIO[4] signal. The boot configuration signal on the
ADDR[9] pin selects between SDOUT and PIO[4] (refer to Section "3.3 Pin multiplex").
SDIN[1]
Input
Serial, Time Division Multiplexed, AC '97 Input Stream
When this pin is used as SDIN[1], pull down by the resister on the board. (Regarding the
value of register, please ask the Engineering Department in Toshiba).
SDIN[0]
Input
Serial, Time Division Multiplexed, AC '97 Input Stream
SDIN[0] shares the pin with the PIO[3] signal. The boot configuration signal on the
ADDR[9] pin selects between SDIN[0] and PIO[3] (refer to Section "3.3 Pin multiplex").
When this pin is used as SDIN[0], pull down by the resister on the board. (Regarding the
value of register, please ask the Engineering Department in Toshiba).
BITCLK
Input
12.288 MHz Serial Data Clock
BITCLK shares the pin with the PIO[2] signal. The boot configuration signal on the
ADDR[9] pin selects between BITCLK and PIO[2] (refer to Section "3.3 Pin multiplex").
When this pin is used as BITCLK, pull down by the resister on the board. (Regarding the
value of register, please ask the Engineering Department in Toshiba).
3.1.10
Interrupt Signals
Signal Name
Type
NMI*
Input
Non-Maskable Interrupt
PU
Non-maskable interrupt signal.
INT[5:0]
Input
External Interrupt Requests
PU
External interrupt request signals.
INT[4:3] share pins with other function signals (refer to Section "3.3 Pin multiplex").
Table 3.1.9 AC-link Interface Signals
Description
Table 3.1.10 Interrupt Signals
Description
3-7
Chapter 3 Signals
Initial State
Selected by
ADDR[9]
L: Low
H: Input
Selected by
ADDR[9]
L: Low
H: High
Selected by
ADDR[9]
L: Low
H: Input
Input
Input
Input
Initial State
Input
Input
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