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7.
External Bus Controller
7.1
Features
The External Bus Controller is used for accessing ROM, SRAM memory, and I/O peripherals. The
features of this bus are described below.
(1) 8 independent channels
(2) Supports access to ROM (mask ROM, page mode ROM, EPROM, EEPROM), SRAM, flash memory,
and I/O peripherals.
(3) Selectable data bus width of 8-bit, 16-bit, 32-bit for each channel
(4) Selectable full-speed, 1/2 speed, 1/3 speed, 1/4 speed for each channel
(5) Programmable timing for each channel. Programmable setup and hold time of address, chip enable,
write enable, and output enable signals.
(6) Supports memory sizes from 1 MB to 1 GB for devices with a 32-bit data bus. Supports memory sizes
from 1 MB to 512 MB for devices with a 16-bit data bus. Supports memory sizes from 1 MB to 256 MB
for devices with an 8-bit data bus.
(7) Supports special DMAC Burst access (address decrement/fixed).
(8) Supports critical word first access of the TX49/H3 core.
(9) Supports page mode memory. Supports 4-, 8-, and 16-page size.
(10) Supports the External Acknowledge Signal (ACK*) and External Ready Signal modes.
(11) Channel 0 can be used as Boot memory. Boot settings can be made from the following selections:
•
Data bus width: 8-bit, 16-bit, 32-bit
•
ACK* output or ACK* input
•
BWE pin (byte enable or byte Write enable)
•
Boot channel clock frequency
Chapter 7 External Bus Controller
7-1
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