Toshiba TX49 TMPR4937 Manual page 114

SYSCLK
CE*/BE*
ADDR [19:0]
OE*
SWE*/BWE*
DATA [31:0]
ACK*/READY
(Output)
Figure 7.3.6 SHWT 1 Wait (Normal Mode, Single Read/Write Cycle)
7.3.7.2 ACK*/READY Input/Output Switching Timing
When in the ACK*/Ready Static mode, the ACK*/Ready signal is always an input signal. When
in the ACK*/Ready Dynamic mode, the ACK*/Ready signal is an input signal when in the
External ACK mode or the Ready mode, but is an output signal in all other modes.
During External ACK mode or Ready mode access, the ACK* signal becomes High-Z at the
cycle where the CE* signal is asserted. At the end of the access cycle, the ACK* signal is output
(driven) again one clock cycle after the CE* signal is deasserted (see Figure 7.3.3 and Figure
7.5.23).
Chapter 7 External Bus Controller
7-14
EBCCRn.PWT:WT=0
EBCCRn.SHWT=1