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13.4.3
PIO Direction Control Register (PIODIR)
31
15
14
13
12
Bit
Mnemonic
Field Name
31:16
Reserved
15 :0
PDIR [15:0]
Direction Control
13.4.4
PIO Open Drain Control Register (XPIOOD)
31
15
14
13
12
Bit
Mnemonic
Field Name
31:16
Reserved
15 :0
POD [15:0]
Open Drain
Control
Reserved
11
10
9
8
PDIR
R/W
0x0000
Port Direction Control [15:0] (Initial value: 0x0000)
Sets the I/O direction of the PIO pin (PIO [15:0]).
0: Input (Reset)
1: Output
Figure 13.4.3 PIO Direction Control Register
Reserved
11
10
9
8
POD
R/W
0x0000
Port Open Drain Control [15:0] (Initial value: 0x0000)
Sets whether to use the PIO pin (PIO [15:0]) as an open drain.
0: Open drain (Reset)
1: Totem pole
Figure 13.4.4 PIO Open Drain Control Register
13-4
Chapter 13 Parallel I/O Port
0xF508
7
6
5
4
Description
0xF50C
7
6
5
4
Description
16
:Type
:Initial value
3
2
1
0
:Type
:Initial value
Read/Write
⎯
R/W
16
:Type
:Initial value
3
2
1
0
:Type
:Initial value
Read/Write
⎯
R/W
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