12.4.5
Interval Timer Mode Register n (TMITMRn)
31
15
14
TIIE
R/W
0
Bit
Mnemonic
Field Name
31:16
Reserved
15
TIIE
Interval Timer
Interrupt Enable
14:1
Reserved
0
TZCE
Interval Timer
Clear Enable
Reserved
Reserved
Timer Interval Interrupt Enable (Default: 0)
Sets Interval Timer TMCPRA Interrupt Enable/Disable.
0: Disable (mask)
1: Enable
Interval Timer Zero Clear Enable (Default: 0)
This bit specifies whether or not to clear the counter to "0" after the count
value matches Compare Register A. Count stops at this value if it is not
cleared.
0: Do not clear
1: Clear
Figure 12.4.5 Interval Timer Mode Register
12-14
Chapter 12 Timer/Counter
TMITMR0 0xF010
TMITMR1 0xF110
TMITMR2 0xF210
Description
16
: Type
: Initial value
1
0
TZCE
R/W : Type
: Initial value
0
Read/Write
⎯
R/W
⎯
R/W