Toshiba TX49 TMPR4937 Manual page 110

7.3.6.1 Normal Mode
When in this mode, the ACK*/Ready signal becomes an ACK* output when it is in the
ACK*/Ready Dynamic mode. The ACK*/Ready signal becomes High-Z when it is in the
ACK*/Ready Static mode.
Wait cycles are inserted according to the EBCCRn.PWT and EBCCRn.WT value at the access
cycle. The Wait cycle count is 0 – 0x3e (becomes the external ACK mode when set to
EBCCRn.PWT: WT = 0x3f).
SYSCLK
CE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY (Output)
7.3.6.2 External ACK Mode
When in this mode, the ACK*/READY pin becomes ACK* input, and the cycle is ended by the
ACK* signal from an external device. ACK* input is internally synchronized. Refer to Section
"7.3.7.4 ACK* Input Timing" for more information regarding timing.
SYSCLK
CE*
ADDR [19:0]
OE*
DATA [31:0]
ACK*/READY(Input)
Chapter 7 External Bus Controller
EBCCRn.PWT:WT=3
Figure 7.3.1 Normal Mode
Figure 7.3.2 External ACK Mode
7-10
expresses indeterminate values
EBCCRn.SHWT=0
represents indeterminate values.
EBCCRn.SHWT=0