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15.4.21 Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524
31
15
14
13
12
MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT
[15]
[14]
[13]
[12]
Bit
Mnemonic
Field Name
⎯
31:16
15:0
MEXT [15:0]
External Request
Mask
Figure 15.4.21 Interrupt Request External Interrupt Mask Register
Reserved
11
10
9
8
[11]
[10]
[9]
[8]
R/W
0x0000
⎯
Reserved
External Interrupt Mask (Default: 0x0000)
These bits specify whether to use the corresponding flag bit as an
external interrupt cause. Interrupt causes are masked when this bit is "0."
0: Mask (reset)
1: Do not mask
15-44
Chapter 15 Interrupt Controller
7
6
5
4
3
[7]
[6]
[5]
[4]
[3]
Explanation
16
: Type
: Default
2
1
0
[2]
[1]
[0]
: Type
: Default
Read/Write
⎯
R/W
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