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Table 9.3.3 Address Signal Mapping (32-bit Data Bus) (2/2)
Row Address Width = 12
Column Address Width = 11
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
25
26
Address
Row Address
25
26
Row Address Width = 13
Column Address Width = 8
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
23
24
Address
Row Address
23
24
Row Address Width = 13
Column Address Width = 9
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
24
25
Address
Row Address
24
25
Row Address Width = 13
Column Address Width = 10
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
25
26
Address
Row Address
25
26
Row Address Width = 13
Column Address Width = 11
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
26
27
Address
Row Address
26
27
Row Address Width = 13
Column Address Width = 12
Address Bit
19
18
ADDR [19:5]
(B0)
(B1)
Column
29
28
Address
Row Address
29
28
15
17
16
14
13
(AP)
25
24
L/H
23
22
25
21
20
19
18
15
17
16
14
13
(AP)
22
21
L/H
24
23
22
21
20
19
18
15
17
16
14
13
(AP)
22
21
L/H
24
23
22
21
20
19
18
15
17
16
14
13
(AP)
22
21
L/H
24
23
22
21
20
19
18
15
17
16
14
13
(AP)
22
25
L/H
24
23
22
21
20
19
18
15
17
16
14
13
(AP)
26
25
L/H
24
23
22
21
20
19
18
9-8
Chapter 9 SDRAM Controller
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
12
11
10
9
8
9
8
7
6
5
17
16
15
14
13
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
7
6
5
4
3
2
12
11
10
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