Interrupt Interface Ac Characteristics - Toshiba TX49 TMPR4937 Manual

Notes:
(1) DMAREQ[n]
Edge Detection: Set the pulse width to 1.1× the GBUSCLK cycle or higher.
Level Detection: There is no AC characteristic definition. Continue asserting DMAREQ[3:0]
(2) DMAACK[n]
The DMAACK[n] signal is synchronous to SDCLK. (It is driven by GUBSCLK inside the chip.
See Chapter 6 for more information.)
The DMAACK[n] signal is asserted by SYSCLK or SDCLK for 3 cycles or more. However, this
is changed by the conditions [1] and [2] below.
[1] DMAC transfer mode (Single Address transfer, Dual Address transfer)
[2] Access time of the device DMAC accesses
SDCLK[n]
DMAACK[n]
•
When driving an external device with SYSCLK
Is asserted by SYSCLK for at least 3 cycles even in the shortest assertion case.
•
When driving an external device with SDCLK
Is asserted by SDCLK for at least 3 cycles even in the shortest assertion case. The AC
characteristics for Single Address transfer with SDRAM are tight, so we do not
recommend Single Address transfer.
(3) DMADONE*
Is asserted for only 1 SYSCLK cycle synchronous to SYSCLK.
21.5.9

Interrupt Interface AC characteristics

Item
INT Input Pulse Width Time
NMI Input Pulse Width Time
until DMAACK[3:0] is received.
(Tc = 0 – 70°C, V
CCIO
Symbol Conditions
t Boot configuration
PW_INT
ADDR[2]=H
Boot configuration
ADDR[2]=L
t Boot configuration
PW_NMI
ADDR[2]=H
Boot configuration
ADDR[2]=L
t /t
PW_INT PW_NMI
Figure 21.5.10 Timing Diagram: INT/NMI Interface
21-12
Chapter 21 Electrical Characteristics
Assertion Time
= 3.3 V ± 0.2 V, V = 1.5 V ± 0.1 V, V
CCInt
Min.
2 × t
MCP
1/2 × t
MCP
× 1.1
t
MCP
1/4 × t
MCP
= 0 V)
SS
Max. Unit
× 1.1 ⎯
ns
× 1.1 ⎯
ns
⎯
ns
× 1.1 ⎯
ns