Block Diagram - Toshiba TX49 TMPR4937 Manual

15.2 Block Diagram

TX49/H3 Core
Internal Timer
Interrupt Request
0
Interrupt
[7]
Request
1
(IP[7:2])
[6:2]
Non-maskable
Interrupt Request
TINTDIS
PCIC
Interrupt Controller
Detection Circuit
[7:2]
Set Interrupt Level
Set Interrupt Mask
Process Priority
Watchdog Timer Interrupt
Flag Register
Polarity Register
Mask Register
Interrupt Control Register
Figure 15.2.1 Interrupt Controller Outline
15-2
Chapter 15 Interrupt Controller
6
External Interrupt Signal (INT[5:0])
1
ECC Error
1
TX49 Write time out Error
2
SIO[1:0]
4
DMA0[3:0]
4
DMA1[3:0]
3
TMR[2:0]
2
ACLC
1
PDMAC0
1
PCIC0
1
PCIERR0
1
PCIPME0
1
ETHERC0
1
ETHERC1
1
NDFMC
1
PCIC1
1
SPI
1
Internal Interrupt Request
Non-maskable Interrupt Signal (NMI*)
(active Low)
Watch-dog timer Interrupt (TMR2)
(active Low)
External Interrupt Request
Internal
Interrupt
Signal
REQ[1]*/INTOUT