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15.4.11 Interrupt Level Register 7 (IRLVL7)
31
Reserved
15
Reserved
Bit
Mnemonic
Field Name
⎯
31:27
26:24
IL31
Interrupt level 31
⎯
23:19
18:16
IL31
Interrupt level 30
⎯
15:11
10:8
IL15
Interrupt level 15
⎯
7:3
27
26
24
IL31
R/W
000
11
10
8
IL15
R/W
000
⎯
Reserved
Interrupt Level of INT [31] (Default: 000)
These bits specify the interrupt level of SPI interrupts.
000: Interrupt level 0 (Interrupt disabled)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Interrupt Level of INT [30] (Default: 000)
These bits specify the interrupt level of DMA1[3] interrupts.
000: Interrupt level 0 (Interrupt disabled)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Interrupt Level of INT [15] (Default: 000)
These bits specify the interrupt level of PDMAC interrupts.
000: Interrupt level 0 (Interrupt disabled)
001: Interrupt level 1
010: Interrupt level 2
011: Interrupt level 3
100: Interrupt level 4
101: Interrupt level 5
110: Interrupt level 6
111: Interrupt level 7
⎯
Reserved
Figure 15.4.11 Interrupt Level Register 7 (1/2)
15-30
Chapter 15 Interrupt Controller
0xF62C
23
19
Reserved
7
3
Reserved
Explanation
18
16
IL30
R/W
: Type
000
: Default
2
0
IL14
R/W
: Type
000
: Default
Read/Write
⎯
R/W
⎯
R/W
⎯
R/W
⎯
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