Table 37. Instruction Summary (Continued)
Instruction and Operation
INIMR
repeat {
(HL) ← ({0000h, C})
B ← B – 1
C ← C+1
HL ← HL+1
} while B ≠ 0
INIR
repeat {
(HL) ← ({00h, BC[15:0]})
B ← B – 1
HL ← HL+1
} while B ≠ 0
INIRX
repeat {
(HL) ← ({00h, DE[15:0]})
BC ← BC – 1
HL ← HL + 1
} while BC ≠ 0
JP cc,Mmn
if cc {
PC ← Mmn {
if .S {ADL ← 0}
else if .L {ADL ← 1}
}
JP (ss)
PC ← ss
if .S {ADL ← 0}
else if .L {ADL ← 1}
JP Mmn
PC ← Mmn {
if .S {ADL ← 0}
else if .L {ADL ← 1}
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.
UM007714-0908
Address Mode
Opcode(s)
Dest Source
(Hex)
ED 92
ED B2
ED C2
C2-FA
(HL)
E9
(IX/Y)
DD/FD E9
C3
®
eZ80
CPU
User Manual
Flags Affected
S
Z
H P/V N
C
—
1
—
—
*
—
—
1
—
—
*
—
—
1
—
—
*
—
— — —
—
— —
— — —
—
— —
— — —
—
— —
CPU Instruction Set
65
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