ZiLOG eZ80 User Manual page 248

LDDR
Load and Decrement with Repeat
Operation
repeat {
(DE) ← (HL)
BC ← BC – 1
DE ← DE – 1
HL ← HL – 1
} while (BC ≠ 0)
Description
The CPU writes the contents of the memory location with address contained in the multi-
byte register HL to the memory location with address contained in the multibyte register
DE. The BC, DE, and HL registers decrement. This operation is repeated until BC decre-
ments to 0.
In Z80 mode, the BC register is 16 bits, which allows the LDDR instruction to repeat a
maximum of 65536 (64 K) times. In ADL mode, the BC register is 24 bits, which allows
the LDDR instruction to repeat a maximum of 16,777,216 (16 M) times.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
LDDR
LDDR.S
LDDR.L
UM007714-0908
Not affected.
Not affected.
Reset.
Reset if BC− 1 = 0; set otherwise.
Reset.
Not affected.
ADL Mode Cycle
— X
— 1
— 0
Opcode (hex)
2 + 3 *
ED, B8
BC
3 + 3 *
52, ED, B8
BC
3 + 3 *
49, ED, B8
BC
®
eZ80 CPU
User Manual
239
CPU Instruction Set