ZiLOG eZ80 User Manual page 177

INDMR
Input from I/O and Decrement with Repeat
Operation
repeat {
(HL) ← ({UU, 00h,C})
B ← B – 1
C ← C – 1
HL ← HL – 1
} while B ≠ 0
Description
The CPU places the contents of register C onto the lower byte of the address bus,
ADDR[7:0], and places a 0 onto the High byte of the address bus, ADDR[15:8]. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU
reads the byte located at I/O address {UU,
places the contents of HL onto the address bus and writes the byte to the memory address
specified by the HL register. The CPU decrements the B, C, and HL registers, and sets the
Z Flag to 1 if the B register is decremented to 0.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
INDMR
INDMR.S
INDMR.L
UM007714-0908
Not affected.
Set if B – 1 = 0; reset otherwise.
Not affected.
Not affected.
Set if msb of data is a logical 1; reset otherwise.
Not affected.
ADL Mode Cycle
— X
— 1
— 0
, C} into CPU memory. The CPU next
00h
Opcode (hex)
2 + 3 * B ED, 9A
3 + 3 * B 52, ED, 9A
3 + 3 * B 49, ED, 9A
®
eZ80 CPU
User Manual
168
CPU Instruction Set