ZiLOG eZ80 User Manual page 271

OTI2R
Output to I/O and Increment with Repeat
Operation
repeat {
({UU, DE[15:0]}) ← (HL)
BC ← BC – 1
DE ← DE+1
HL ← HL+1
} while BC ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to I/O address {UU, DE[15:0]}. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The BC reg-
ister decrements. The DE and HL registers increment. The instruction repeats until register
BC equals 0.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
OTI2R
OTI2R.S
OTI2R.L
Note
This instruction operates differently in eZ80190 device product. In the eZ80190, operation
is:
UM007714-0908
Not affected.
Set if BC – 1 = 0; reset otherwise.
Not affected.
Not affected.
Set if msb of data is logical 1; reset otherwise.
Not affected.
ADL Mode Cycle
— X
— 1
— 0
Opcode (hex)
2 + 3 * B ED, B4
3 + 3 * B 52, ED, B4
3 + 3 * B 49, ED, B4
®
eZ80 CPU
User Manual
262
CPU Instruction Set