ZiLOG eZ80 User Manual page 249

LDI
Load and Increment
Operation
(DE) ← (HL)
BC ← BC – 1
DE ← DE+1
HL ← HL+1
Description
The CPU writes the contents of the memory location with address contained in the multi-
byte register HL to the memory location with address contained in the multibyte register
DE. The BC register decrements. The DE and HL registers increment.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
LDI
LDI.S
LDI.L
UM007714-0908
Not affected.
Not affected.
Reset.
Reset if BC− 1 = 0; set otherwise.
Reset.
Not affected.
ADL Mode Cycle Opcode (hex)
— X
— 1
— 0
5
ED, A0
6
52, ED, A0
6
49, ED, A0
®
eZ80 CPU
User Manual
240
CPU Instruction Set