ZiLOG eZ80 User Manual page 94

ADC HL, rr
ADD with Carry
Operation
HL ← HL+rr+C
Description
The rr operand is any of the multibyte registers BC, DE, or HL. The rr operand and the
Carry Flag (C in the F register) are added to the contents of the HL register. The result is
stored in the HL register.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic
ADC
ADC.S
ADC.L
identifies the BC, DE, or HL register and is assembled into one of the opcodes in
kk
Table 39.
UM007714-0908
Set if result is negative; reset otherwise.
Set if result is 0; reset otherwise.
Set if carry from bit 11; reset otherwise.
Set if overflow; reset otherwise.
Reset.
Set if carry from MSB; reset otherwise.
Operand ADL Mode
HL,ss X
HL,ss 1
HL,ss 0
Cycle Opcode (hex)
2
ED, kk
3
52, ED, kk
3
49, ED, kk
®
eZ80 CPU
User Manual
85
CPU Instruction Set