ZiLOG eZ80 User Manual page 42

Table 20. RETN Instruction
User Code
RETN
RETN
RETN.S
RETN.L
RETN.L
UM007714-0908
ADL Assembled
Mode Code
0
RETN
assembles to
ED 45
1
RETN
assembles to
ED 45
0
—
0
RETN.LIS
assembles to
49 ED 45
1
RETN.LIL
assembles to
5B ED 45
Operation
The starting program counter is {MBASE,
PC[15:0]}. Pop a 2-byte return address from
{MBASE, SPS} into PC[15:0]. The ADL mode bit
remains cleared to 0. The ending program counter
is {MBASE, PC[15:0]}. IEF1 ← IEF2.
The starting program counter is PC[23:0]. Pop a 3-
byte return address from SPL into PC[23:0]. The
ADL mode bit remains set to 1. The ending
program counter is PC[23:0]. IEF1 ← IEF2.
Because RETI.S is an invalid suffix, RETN.L must
be used in all mixed-memory mode applications.
IEF1 ← IEF2.
The starting program counter is {MBASE,
PC[15:0]}. Pop a byte from SPL into ADL to set
memory mode (03h = ADL, 02h = Z80).
if ADL mode {
Pop the upper byte of the return address from SPL
into PC[23:16].
Pop 2 LS bytes of the return address from {MBASE,
SPS} into PC[15:0]. The ending program counter is
PC[23:0].
}
else Z80 mode {
Pop a 2-byte return address from {MBASE,SPS}
into PC[15:0]. The ending program counter is
{MBASE, PC[15:0]}. IEF1 ← IEF2.
}
The starting program counter is PC[23:0]. Pop a
byte from SPL into ADL to set memory mode
(03h = ADL, 02h = Z80).
if ADL mode {
Pop 3-byte return address from SPL into PC[23:0].
The ending program counter is PC[23:0].
}
else Z80 mode {
Pop a 2-byte return address from SPL into PC[15:0].
The ending program counter is {MBASE,
PC[15:0]}. IEF1 ← IEF2.
}
®
eZ80 CPU
User Manual
Memory Mode Switching
33