ZiLOG eZ80 User Manual page 147

DEC rr
Decrement
Operation
rr ← rr – 1
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The value contained
in the specified register is decremented by 1.
Condition Bits Affected
None.
Attributes
Mnemonic
DEC
DEC.S
DEC.L
identifies the BC, DE, or HL register and is assembled into one of the opcodes indi-
kk
cated in
Table 53. Register and kk Opcodes for DEC rr Instruction (hex)
Register kk
BC
DE
HL
UM007714-0908
Operand ADL Mode
X
rr
1
rr
0
rr
Table 53.
0B
1B
2B
Cycle Opcode (hex)
1
kk
2
52, kk
2
49, kk
®
eZ80 CPU
User Manual
138
CPU Instruction Set