ZiLOG eZ80 User Manual page 38

Table 16. JP (rr) Instruction (Continued)
User Code
JP (rr)
JP.L (rr)
JP.S (rr)
Table 17. RST n Instruction
User Code
RST n
RST n
RST.S n
UM007714-0908
ADL Assembled
Mode Code
1
JP (rr)
assembles to
E9 or DD/FD
E9
1
JP.LIL (rr)
assembles to
5B E9 or
5B DD/FD E9
1
JP.SIL (rr)
assembles to
52E9 or
52DD/FD E9
ADL Assembled
Mode Code
0
RST n
assembles to
CD nn
1
RST n
assembles to
CD nn
0
RST.SIS n
assembles to
40 CD nn
Operation
The starting program counter is PC[23:0]. Write the
3-byte value stored in rr[23:0] to PC[23:0]. The
ADL mode bit remains set to 1. The ending
program counter is PC[23:0] = rr[23:0].
This operation is the same as the previous
operation. The .LIL extension does not affect
operation when beginning in ADL mode.
The starting program counter is PC[23:0]. Write the
2-byte value stored in rr[15:0] to PC[15:0]. Reset
ADL mode bit to 0. The ending program counter is
{MBASE, PC[15:0]} = {MBASE, rr[15:0]}.
Operation
The starting program counter is {MBASE,
PC[15:0]}. Push the 2-byte return address,
PC[15:0], onto the {MBASE,SPS} stack. The ADL
mode bit remains cleared to 0. Write {00h, nn} to
PC[15:0]. The ending program counter is {MBASE,
PC[15:0]} = {MBASE, 00h, nn}.
The starting program counter is PC[23:0]. Push the
3-byte return address, PC[23:0], onto the SPL
stack. The ADL mode bit remains set to 1. Write
{0000h, nn} to PC[23:0]. The ending program
counter is PC[23:0] = {0000h, nn}.
The starting program counter is {MBASE,
PC[15:0]} Push the 2-byte return address,
PC[15:0], onto the {MBASE, SPS} stack. Push a
02h byte onto the SPL stack, indicating an
interrupt from Z80 mode (ADL = 0). The ADL mode
bit remains cleared to 0. Write {00h, nn} to
PC[15:0].The ending program counter is {MBASE,
PC[15:0]} = {MBASE, 00h, nn}.
®
eZ80 CPU
User Manual
Memory Mode Switching
29