ZiLOG eZ80 User Manual page 239

LD rr, Mmn
Load Register
Operation
rr ← Mmn
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The immediate
operand, Mmn, is written to the multibyte rr register.
Condition Bits Affected
None.
Attributes
Mnemonic Operand
LD
LD
LD.LIL
LD.SIS
identifies the BC, DE, HL, or SPI register and is assembled into one of the opcodes
kk
indicated in
Table 71. Register and kk Opcodes for LD rr, Mmn Instruction (hex)
Register kk
BC
DE
HL
UM007714-0908
ADL Mode Cycle Opcode (hex)
0
ss,mn
1
ss,Mmn
0
ss,Mmn
1
ss,mn
Table 71.
01
11
21
3
kk, nn, mm
4
kk, nn, mm, MM
5
5B, kk, nn, mm, MM
4
40, kk, nn, mm
®
eZ80 CPU
User Manual
230
CPU Instruction Set