ZiLOG eZ80 User Manual page 178

INDR
Input from I/O and Decrement with Repeat
Operation
repeat {
(HL) ← ({UU, BC[15:0]})
B ← B – 1
HL ← HL – 1
} while B ≠ 0
Description
The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus,
ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O
addresses. The CPU reads the byte located at I/O address {UU, BC[15:0]} into CPU mem-
ory. The CPU next places the contents of HL onto the address bus and writes the byte to
the memory address specified by the HL register. Next, the CPU decrements the B and HL
registers, and sets the Z Flag to 1 if the B register is decremented to 0. The instruction
repeats until the B register equals 0.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
INDR
INDR.S
INDR.L
UM007714-0908
Not affected.
Set of B – 1 = 0; reset otherwise.
Not affected.
Not affected.
Set if msb of data is a logical 1; reset otherwise.
Not affected.
ADL Mode Cycle
— X
— 1
— 0
Opcode (hex)
2 + 3 * B ED, BA
3 + 3 * B 52, ED, BA
3 + 3 * B 49, ED, BA
®
eZ80 CPU
User Manual
169
CPU Instruction Set