ZiLOG eZ80 User Manual page 269

OTDR
Output to I/O and Decrement
Operation
repeat {
({UU, BC[15:0]}) ← (HL)
B ← B – 1
HL ← HL – 1
} while B ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B and
HL registers are decremented. The instruction repeats until register B equals 0.
Condition Bits Affected
S
Z
H
P/V
N
C
Attributes
Mnemonic Operand
OTDR
OTDR.S
OTDR.L
UM007714-0908
Not affected.
Set if B – 1 = 0; reset otherwise.
Not affected.
Not affected.
Set if msb of data is logical 1; reset otherwise.
Not affected.
ADL Mode Cycle
— X
— 1
— 0
Opcode (hex)
2 + 3 * B ED, BB
3 + 3 * B 52, ED, BB
3 + 3 * B 49, ED, BB
®
eZ80 CPU
User Manual
260
CPU Instruction Set